The present invention relates to semiconductor devices and, more particularly, to contact structures included in semiconductor devices.
Semiconductor devices such as field effect transistors (FETs), for example, typically include metal contacts. The close proximity of a metal gate contact to the one or more of the source/drain (S/D) metal contacts can induce a parasitic capacitance effect. As demands for semiconductor devices with reduced footprints continue, the contact gate pitch is further scaled to reduced dimensions, which increase the parasitic capacitance between the gate contact and the S/D contacts.